Rainbow Electronics AT83C26 - Manual (Page 17)

17
7511B–SCR–10/05
AT83C26
Transparent mode arbitration system
The first between IO and CIO to force a low level becomes the master.
The slave signal is grounded after t1 delay:
t1 max = 2* (CLK period).
Figure 10. Bidirectional mode
The minimum delay for a pulse at 0 or 1 to be detected is between 0.5 and 1.5 CLK period
(depending on arrival time).
If IO and CIO are both grounded, CIO becomes the master.
The minimum delay to switch of master without electrical conflict is equal to:
t2 min = 4 * (CLK period) + 2 * (DCCLK period) * (CLK period).
If a master switch appears before this minimum delay, the electrical conflict delay is:
t2 = 2 * (DCCLK period) * (CLK period)
Figure 11. Electrical conflict
master
master
t1 t1
IO
CIO
t1 t1
t2
slave
slave
master
master
t1
IO
CIO
t2
slave
slave
CIO pad becomes output