User i/os by bank – Xilinx DS610 User Manual
Page 96
Spartan-3A DSP FPGA Family: Pinout Descriptions
DS610 (v3.0) October 4, 2010
Product Specification
96
User I/Os by Bank
indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The
AWAKE pin is counted as a dual-purpose I/O.
Table 69: User I/Os Per Bank for the XC3SD3400A in the FG676 Package
Package
Edge
I/O Bank
Maximum I/Os
and
Input-Only
All Possible I/O Pins by Type
I/O
INPUT
DUAL
CLK
Top
0
111
82
11
1
9
8
Right
1
123
67
8
30
10
8
Bottom
2
112
68
6
21
9
8
Left
3
123
97
9
0
9
8
TOTAL
469
314
34
52
37
32
Notes:
1.
26 VREF are on INPUT pins.