Xilinx DS610 - Manual (Page 36)

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010 www.xilinx.com
Product Specification 36
LVCMOS25 Slow 2 76 76
4 46 46
6 33 33
8 24 24
12 18 18
16 – 11
24 – 7
Fast 2 18 18
4 14 14
6 6 6
8 6 6
12 3 3
16 – 3
24 – 2
QuietIO 2 76 76
4 60 60
6 48 48
8 36 36
12 36 36
16 – 36
24 – 8
Table 28: Recommended Simultaneously Switching
Outputs per V
CCO
/GND Pair (V
CCAUX
= 3.3V) (Cont’d)
Signal Standard
(IOSTANDARD)
Package Type
CS484, FG676
Top, Bottom
(Banks 0, 2)
Left, Right
(Banks 1, 3)
LVCMOS18 Slow 2 64 64
4 34 34
6 22 22
8 18 18
12 – 13
16 – 10
Fast 2 18 18
4 9 9
6 7 7
8 4 4
12 – 4
16 – 3
QuietIO 2 64 64
4 64 64
6 48 48
8 36 36
12 – 36
16 – 24
LVCMOS15 Slow 2 55 55
4 31 31
6 18 18
8 – 15
12 – 10
Fast 2 25 25
4 10 10
6 6 6
8 – 4
12 – 3
QuietIO 2 70 70
4 40 40
6 31 31
8 – 31
12 – 20
Table 28: Recommended Simultaneously Switching
Outputs per V
CCO
/GND Pair (V
CCAUX
= 3.3V) (Cont’d)
Signal Standard
(IOSTANDARD)
Package Type
CS484, FG676
Top, Bottom
(Banks 0, 2)
Left, Right
(Banks 1, 3)