Xilinx DS610 - Manual (Page 101)

Spartan-3A DSP FPGA Family: Pinout Descriptions
DS610 (v3.0) October 4, 2010 www.xilinx.com
Product Specification 101
Revision History
The following table shows the revision history for this document.
Date Version Revision
04/02/07 1.0 Initial Xilinx release.
05/25/07 1.1 Updates to Table 59 , Table 63 , Table 64 , Table 65 , Table 66 , Table 67 , Table 68 , Table 69 . Corrected
VREF pins in XC3S1800A FG676 ( Table 70 ). Updated FG676 package footprints for XC3SD1800A
FPGA ( Figure 16 ) and XC3SD3400A FPGA ( Figure 17 ). Minor edits.
06/18/07 1.2 Updated for Production release.
07/16/07 2.0 Added Low-power options. Added advance thermal data to Table 62 .
06/02/08 2.1 Added Package Overview section. Updated Thermal Characteristics in Table 62 . Corrected name for
AB14 in CS484 in Table 63 . Updated links.
03/11/09 2.2 Corrected bank designation for SUSPEND to VCCAUX.
10/04/10 3.0 Revision update to match other data sheet modules.