Xilinx DS610 - Manual (Page 56)

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010 www.xilinx.com
Product Specification 56
Serial Peripheral Interface (SPI) Configuration Timing
X-Ref Target - Figure 13
Figure 13: Waveforms for Serial Peripheral Interface (SPI) Configuration
Table 52: Timing for Serial Peripheral Interface (SPI) Configuration Mode
Symbol Description Minimum Maximum Units
T
CCLK1
Initial CCLK clock period See Table 46
T
CCLKn
CCLK clock period after FPGA loads ConfigRate setting See Table 46
T
MINIT
Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the
rising edge of INIT_B 50 – ns
T
INITM
Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the
rising edge of INIT_B 0 – ns
T
CCO
MOSI output valid delay after CCLK falling edge See Table 50
T
DCC
Setup time on DIN data input before CCLK rising edge See Table 50
T
CCD
Hold time on DIN data input after CCLK rising edge See Table 50
T
DH
T
DSU
Command
(msb)
T
V
T
CSS
<1:1:1>
INIT_B
M[2:0]
T
MINIT
T
INITM
DIN
CCLK
(Input)
T
CCLK n
T
CCLK1
VS[2:0]
(Input)
New ConfigRate active
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
<0:0:1>
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.
T
CCLK1
T
MCCL n
T
MCCH n
(Input)
Data Data Data Data
CSO_B
MOSI
T
CCO
T
MCCL1
T
MCCH1
T
DCC
T
CCD
(Input)
PROG_B
PUDC_B
(Input)
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
DS529-3_06_102506
(Open-Drain)
Shaded values indicate specifications on attached SPI Flash PROM.
Command
(msb-1)