NXP Semiconductors PCA9665 - Manual (Page 64)

PCA9665_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 7 December 2006 64 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I 2 C-bus controller
External master receiver reads data from PCA9665.
(1) As defined in I2CADR register.
(2) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0] ≤ 68).
Fig 25. Bus timing diagram; Buffered Slave Transmitter mode
n byte (2)
ACK
SCL
SDA
INT
START
condition
7-bit address (1)
R/W = 1
from slave PCA9665
first byte (2)
ACK no ACK
STOP
condition
002aab269 from master receiver
interrupt
interrupt
Slave PCA9665 is written to by external master transmitter.
(1) As defined in I2CADR register.
(2) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0] ≤ 68).
Fig 26. Bus timing diagram; Buffered Slave Receiver mode
n byte (2)
ACK
SCL
SDA
INT
START
condition
7-bit address (1)
R/W = 0
from slave PCA9665
first byte (2)
ACK ACK
STOP
condition
002aab270
interrupt interrupt
(after STOP)
interrupt
Fig 27. Bus timing diagram; Software Reset Call
ACK
SCL
SDA
INT
START
condition
7-bit SWRST
Call address
R/W = 0
from slave PCA9665
first byte = 0xA5
ACK
STOP
condition
002aab488
interrupt
(after STOP)
interrupt
second byte = 0x5A
ACK