Figure 8, Pca9665, Nxp semiconductors – NXP Semiconductors PCA9665 User Manual
Page 23
PCA9665_2
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 7 December 2006
23 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
(1) See
(2) Defined state when a single byte is received and an ACK is sent (AA = 1).
(3) Defined state when a single byte is received and a NACK is sent (AA = 0).
(4) Master Transmitter Byte mode is entered when MODE = 0. Master Transmitter Buffered mode is entered when MODE = 1.
Fig 8.
Format and states in the Master Receiver Byte mode (MODE = 0)
08h
S
SLA
R
A
DATA
A
P
40h
50h
F8h
MR
10h
S
SLA
R
W
to Master Transmitter mode
entry = MT
(4)
A
P
48h
F8h
002aab025
A
38h
other MST
continues
A or A
38h
other MST
continues
A
other MST
continues
successful
reception from
a Slave Transmitter
next transfer started with a
repeated START condition
Not Acknowledge received after
the slave address
arbitration lost in slave address
or Acknowledge bit
arbitration lost and addressed as slave
n
This number (contained in I2CSTA) corresponds
to a defined state of the I
2
C-bus.
(1)
DATA
A
any number of data bytes and
their associated Acknowledge bits
from master to slave
from slave to master
DATA
A
58h
(2)
(3)
B0h
68h
to corresponding states in Slave Transmitter mode
to corresponding states in Slave Receiver mode
D8h
to corresponding states in Slave Receiver mode (General Call)