NXP Semiconductors PCA9665 - Manual (Page 50)

PCA9665_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 7 December 2006 50 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I 2 C-bus controller
6. More sequences (program I2CCOUNT register, load data bytes in I2CDAT buffer,
write the I2CCON register to send the data to the I 2 C-bus, read the I2CSTA register
when sequence has been executed) can be performed as long as the master
acknowledges the bytes sent by the PCA9665 and AA = 1. Slave Transmitter Buffered
mode ends when the I
2 C-bus master does not acknowledge a byte or when the
PCA9665 goes to Non-addressed Slave mode.
8.5.4 Buffered Slave Receiver mode
1. An interrupt is asserted and the SI bit is set in the I2CCON register when the
PCA9665‘s own slave address has been detected in the I 2 C-bus (AA = 1, own slave
address defined in the I2CADR register). In Slave Receiver mode, R/W = 0.
2. Program the I2CCOUNT register with the number of bytes that needs to be read from
a master device in the I 2 C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used in
Receiver mode to let the PCA9665 know if the last byte received must be
acknowledged or not.
LB = 0: Last received byte is acknowledged and another sequence can be executed.
LB = 1: Last received byte is not acknowledged.
3. The I2CCON is programmed to clear the previous Interrupt. The PCA9665 receives
data from the I 2 C-bus master. MODE bit must be set to ‘1’ each time a write to the
I2CCON register is performed.
4. When the sequence has been executed (BC[6:0] bytes have been received or the
master sent a STOP or Repeated START command), an Interrupt is asserted and the
SI bit is set in the I2CCON register. The I2CSTA register contains the status of the
transmission and the I2CCOUNT register contains the number of bytes that have
been received. I2CDAT buffer contains all the data that has been received and can be
read by the microcontroller.
5. More sequence (program the I2CCOUNT register, write to the I2CCON register, read
the I2CDAT buffer) can be performed as long as a STOP or a Repeated START
command has not been sent by the I
2 C-bus master. Slave Receiver Buffered mode
ends when the I 2 C-bus master sends a STOP or Repeated START command, or
when the PCA9665 does not acknowledge the received bytes any more.
8.5.5 Example: Read 128 bytes in two 64-byte sequences of an EEPROM
(I 2 C-bus address = A0h for write operations and A1h for read operations)
starting at Location 08h
1. Program I2CCOUNT = 02h (2 bytes to be sent): I 2 C-bus slave address and memory
allocation.
2. Write A0h (I 2 C-bus slave address and write command) and 08h (Location) into the
I2CDAT register.
3. Program I2CCON with STA = 1, STO = SI = 0, MODE = 1.
– the PCA9665 sends a START command
– the PCA9665 sends an interrupt, sets SI = 1 and updates I2CSTA register
– I2CSTA reads 08h
4. Program I2CCON with STA = STO = SI = 0, MODE = 1.
– I 2 C-bus slave address A0h, then EEPROM sub address 08h is sent on the bus