NXP Semiconductors PCA9665 - Manual (Page 49)

PCA9665_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 7 December 2006 49 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I 2 C-bus controller
3. Program I2CCON register to initiate the Master Receiver Buffered sequence. In
Master mode, if STA = 1, a START command is sent. An interrupt will be asserted and
the SI bit is set in the I2CCON register after the START has been sent. The I2CSTA
register contains the status of the transmission. MODE bit must be set to ‘1’ each time
a write to the I2CCON register is performed.
4. After reading the I2CSTA status register, the I2CCON is programmed with STA = 0.
That clears the previous Interrupt. If a START command has been previously sent, the
I
2 C-bus address + R/W = 1 byte that has been loaded into the buffer is sent to the
I 2 C-bus, the PCA9665 then becomes a master receiver device and starts receiving
data from the addressed slave device.
Remark: The PCA9665 is already a master receiver device if a buffered sequence
has been previously executed.
5. When the sequence has been executed, an Interrupt is asserted and the SI bit is set
in the I2CCON register. The I2CSTA register contains the status of the transmission
and the I2CCOUNT register contains the number of bytes that have been received.
I2CDAT buffer contains all the data that has been received and can be read by the
microcontroller.
6. More sequences (program the I2CCOUNT register, write to the I2CCON register, read
the I2CSTA register when sequence has been executed, read the I2CDAT buffer) can
be performed as long as a STOP or a Repeated START command has not been sent.
To be able to end the reception, the last buffered sequence must be performed with
LB = 1. Master Receiver Buffered mode ends when the I2CCOUNT register is
programmed with STO = 1.
8.5.3 Buffered Slave Transmitter mode
1. An interrupt is asserted and the SI bit is set in the I2CCON register when the
PCA9665’s own slave address has been detected on the I 2 C-bus (AA = 1, own slave
address defined in the I2CADR register). In Slave Transmitter mode, R/W = 1.
2. Program the I2CCOUNT register with the number of bytes that need to be sent to the
I 2 C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used for Receiver Buffered
mode only.
3. Load the data bytes in I2CDAT buffer. The different bytes to be sent will be stored in
the PCA9665 buffer. There is no protection against writing over a buffer’s boundary. If
more than 68 bytes are written to the buffer, the data at address 00h will be
overwritten. The number of bytes that needs to be loaded in I2CDAT is equal to
BC[6:0] in the I2CCOUNT register. The number of data bytes sent is equal to BC[6:0],
therefore, if the number of data bytes loaded is greater than BC[6:0], the additional
data will not be sent. If the number of data bytes written to the buffer is less than
BC[6:0], the PCA9665 will still send out BC[6:0] data bytes.
4. The I2CCON is programmed to clear the previous Interrupt. The bytes loaded into the
buffer are sent to the I 2 C-bus. MODE bits must be set to ‘1’ each time a write to the
I2CCON register is performed.
5. When the sequence has been executed (BC[6:0] bytes sent or the master sent a
NACK), an Interrupt is asserted and the SI bit is set in the I2CCON register. The
I2CSTA register contains the status of the transmission and the I2CCOUNT register
contains the number of bytes that have been sent to the I
2 C-bus.