NXP Semiconductors PCA9665 - Manual (Page 33)

PCA9665_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 7 December 2006 33 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I 2 C-bus controller
(1) See Table 35
(2) Serial interrupt that occurs when BC[6:0] = 01. No serial interrupt if BC[6:0] > 01.
(3) Defined state when the number of bytes sent is equal to the value in I2CCOUNT register and an ACK has been received for
all the bytes sent.
(4) Defined state when a NACK received while number of bytes sent is lower than or equal to value in I2CCOUNT register.
(5) Master Receiver Byte mode is entered when MODE = 0. Master Receiver Buffered mode is entered when MODE = 1.
Remark: The master should never transmit its own slave address.
Fig 11. Format and states in the Master Transmitter Buffered mode (MODE = 1)
08h
S SLA W A DATA A P
28h F8h
MT
10h
S SLA W
R
to MST/REC mode
entry = MR (5) A P
30h F8h
A P
20h F8h
002aab659
A or A
38h
other MST
continues
A or A
38h
other MST
continues
A
B0h
other MST
continues
68h
to corresponding states in Slave Transmitter mode
to corresponding states in Slave Receiver mode
successful
transmission
to a Slave Receiver
next transfer started with a
repeated START condition
Not Acknowledge received after
the slave address
Not Acknowledge received after
a data byte
arbitration lost in slave address
or data byte
arbitration lost and addressed as slave
n
This number (contained in I2CSTA) corresponds
to a defined state of the I
2 C-bus. (1)
DATA A
any number of data bytes and
their associated Acknowledge bits
from master to slave
from slave to master D8h to corresponding states in Slave Receiver mode (General Call)
(3)
(4)
18h
(2)