Motorola MVME2300 Series - Manual (Page 93)

Functional Description
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Configuration mechanism #1 uses an address register/data register format.
Performing a configuration access is a two-step process. The first step is to
place the address of the configuration cycle within the
CONFIG_ADDRESS register. Note that this action does not generate any
cycles on the PCI bus. The second step is to either read or write
configuration data into the CONFIG_DATA register. If the
CONFIG_ADDRESS register has been set up correctly, the Raven will
pass this access on to the PCI bus as a configuration cycle.
The addresses of the CONFIG_ADDRESS and CONFIG_DATA registers
are actually embedded within PCI I/O space. If the CONFIG_ADDRESS
register has been set incorrectly or the access to either the
CONFIG_ADDRESS or CONFIG_DATA register is not 1,2, or 4 bytes
wide, the Raven will pass the access on to PCI as a normal I/O Space
transfer.
The CONFIG_ADDRESS register is located at offset $CF8 from the
bottom of PCI I/O space. The CONFIG_DATA register is located at offset
$CFC from the bottom of PCI I/O space. The Raven address decode logic
has been designed such that MSADD3 and MSOFF3 must be used for
mapping to PCI Configuration (consequently I/O) space. The
MSADD3/MSOFF3 register group is initialized at reset to allow PCI I/O
access starting at address $80000000. The powerup location (that is, little-
endian disabled) of the CONFIG_ADDRESS register is $80000CF8, and
the CONFIG_DATA register is located at $80000CFC.
The CONFIG_ADDRESS register must be prefilled with four fields:
1. Register Number
2. Function Number
3. Device Number
4. Bus Number
The Register Number and Function Number are passed along to the PCI
bus as portions of the lower address bits.
When performing a configuration cycle, the Raven uses the upper 20
address bits as IDSEL lines. During the address phase of a configuration
cycle, only one of the upper address bits will be set. The device that has its