Motorola MVME2300 Series - Manual (Page 112)

2-42 Computer Group Literature Center Web Site
Raven PCI Bridge ASIC
2
If the SMA or RTA bits are set, the register is defined by the following
figure:
WP Write-Post Completion. This bit is set when the PCI
master detects an error while completing a write-post
transfer.
MIDx MPC Master ID. Contains the ID of the MPC master
which originated the transfer in which the error occurred.
The encoding scheme is identical to that used in the GCSR
register
COMMx PCI Command. Contains the PCI command of the PCI
transfer in which the error occurred.
BYTEx PCI Byte Enable. Contains the PCI byte enables of the
PCI transfer in which the error occurred. A set bit
designates a selected byte.
Address $FEFF002C
Bit
0 1 2 3 4 5 6 7 8 9
1
0 1
1 1
2 1
3 1
4 1
5 1
6 1
7 1
8 1
9 2
0 2
1 2
2 2
3 2
4 2
5 2
6 2
7 2
8 2
9 3
0 3
1
Name MERAT
WP MID
1
MID
0
COMM
3
COMM
2
COMM
1
COMM
0
BYTE7 BYTE6 BYTE5 BYTE4 BYTE3 BYTE2 BYTE1 BYTE0
Operation R R
R R R R R R R R R R R R R R R R
Reset $00 $00
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0