Motorola MVME2300 Series - Manual (Page 123)

Raven Registers
http://www.motorola.com/computer/literature 2-53
2
RES Reserved. This bit is hard-wired to 0.
IOBA I/O Base Address. These bits define the I/O space base
address of the MPIC control registers. The IOBASE
decoder is disabled when the IOBASE value is zero.
Memory Base Register
This register controls the mapping of the MPIC control registers in PCI
memory space.
IO/MEM IO Space Indicator. This bit is hard-wired to a logic 0 to
indicate PCI memory space.
MTYPx Memory Type. These bits are hard-wired to 0 to indicate
that the MPIC registers can be located anywhere in the 32-
bit address space
PRE Prefetch. This bit is hard-wired to 0 to indicate that the
MPIC registers are not prefetchable.
MEMBA Memory Base Address. These bits define the memory
space base address of the MPIC control registers. The
MBASE decoder is disabled when the MBASE value is
zero.
Offset $14
Bit 3
1 3
0 2
9 2
8 2
7 2
6 2
5 2
4 2
3 2
2 2
1 2
0 1
9 1
8 1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 9 8 7 6 5 4 3 2 1 0
Name MEMBASE
MEMBA
PRE MT
Y
P
1
MT
Y
P
0
IO/M
EM
Operation R/W R
R R R R
Reset $0000 $0000
0 0 0 0