Motorola MVME2300 Series - Manual (Page 86)

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Raven PCI Bridge ASIC
2
The slave will honor only the Linear Incrementing addressing mode. The
slave will perform a disconnect with data if any other mode of addressing
is attempted.
Device Selection
The PCI slave will always respond to valid decoded cycles as a medium
responder.
Target-Initiated Termination
The PCI slave normally strives to complete transactions without issuing
disconnects or retries.
One exception is when the slave performs configuration cycles. All
configuration cycles are terminated with a disconnect after one data beat
has been transferred. Another exception is the issue of a disconnect when
asked to perform a transaction with byte enable ‘holes’.
Fast Back-to-Back Transactions
The PCI slave supports both of the fundamental target requirements for
fast back-to-back transactions. The PCI slave meets the first criteria of
being able to successfully track the state of the PCI bus without the
existence of an IDLE state between transactions. The second criteria,
associated with signal turn-around timing, is met by default since the slave
functions as a medium responder.
Latency
The PCI slave has no hardware mechanisms in place to guarantee that the
initial and subsequent target latency requirements are met. This is typically
not a problem, since the bandwidth of the MPC bus far exceeds the
bandwidth of the PCI bus. The Raven MPC arbiter has been designed to
give the highest priority to its own transactions, which further reduces PCI
bus latency.
Exclusive Access
The PCI slave has no mechanism to support exclusive access.