Motorola MVME2300 Series Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for MVME2300 Series Motorola
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 282 |
| Size: | 2.61 MB |
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Document Outline
- Contents
- List of Figures
- List of Tables
- About This Manual
- Board Description and Memory Maps
- Introduction
- Overview
- Summary of Features
- System Block Diagram
- Functional Description
- Programming Model
- ISA Local Resource Bus
- Raven PCI Bridge ASIC
- Introduction
- Features
- Block Diagram
- Functional Description
- Raven Registers
- MPC Registers
- Vendor ID/Device ID Registers
- Revision ID Register
- General Control-Status/Feature Registers
- MPC Arbiter Control Register
- Prescaler Adjust Register
- MPC Error Enable Register
- MPC Error Status Register
- MPC Error Address Register
- MPC Error Attribute Register - MERAT
- PCI Interrupt Acknowledge Register
- MPC Slave Address (0,1 and 2) Registers
- MPC Slave Address (3) Register
- MPC Slave Offset/Attribute (0,1 and 2) Registers
- MPC Slave Offset/Attribute (3) Registers
- General-Purpose Registers
- PCI Registers
- MPC Registers
- Raven Interrupt Controller
- Features
- Architecture
- Block Diagram Description
- MPIC Registers
- RavenMPIC Registers
- Feature Reporting Register
- Global Configuration Register
- Vendor Identification Register
- Processor Init Register
- IPI Vector/Priority Registers
- Spurious Vector Register
- Timer Frequency Register
- Timer Current Count Registers
- Timer Base Count Registers
- Timer Vector/Priority Registers
- Timer Destination Registers
- External Source Vector/Priority Registers
- External Source Destination Registers
- Raven-Detected Errors Vector/Priority Register
- Raven-Detected Errors Destination Register
- Interprocessor Interrupt Dispatch Registers
- Interrupt Task Priority Registers
- Interrupt Acknowledge Registers
- End-of-Interrupt Registers
- Programming Notes
- Architectural Notes
- Falcon ECC Memory Controller Chip Set
- Introduction
- Features
- Block Diagrams
- Functional Description
- Programming Model
- CSR Architecture
- Register Summary
- Detailed Register Bit Descriptions
- Vendor/Device Register
- Revision ID/ General Control Register
- DRAM Attributes Register
- DRAM Base Register
- CLK Frequency Register
- ECC Control Register
- Error Logger Register
- Error Address Register
- Scrub/Refresh Register
- Refresh/Scrub Address Register
- ROM A Base/Size Register
- ROM B Base/Size Register
- DRAM Tester Control Registers
- 32-Bit Counter
- Test SRAM
- Power-Up Reset Status Register 1
- Power-Up Reset Status Register 2
- External Register Set
- Software Considerations
- Universe (VMEbus to PCI) Chip
- Programming Details
- Related Documentation
- Glossary
- Index