Motorola MVME2300 Series - Manual (Page 155)

Raven Interrupt Controller
http://www.motorola.com/computer/literature 2-85
2
Dispatch register has two addresses. These registers are considered to be
per-processor registers and there is one address per processor. Reading
these registers returns zeros.
P1 Processor 1. The interrupt is directed to processor 1.
P0 Processor 0. The interrupt is directed to processor 0.
Interrupt Task Priority Registers
There is one Task Priority register per processor. Priority levels from 0
(lowest) to 15 (highest) are supported. Setting the Task Priority register to
15 masks all interrupts to this processor. Hardware will set the task register
to $F when it is reset, or when the Init bit associated with this processor is
written to a 1.
Offset Processor 0 $20080
Processor 1 $21080
Bit 3
1 3
0 2
9 2
8 2
7 2
6 2
5 2
4 2
3 2
2 2
1 2
0 1
9 1
8 1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 9 8 7 6 5 4 3 2 1 0
Name INTERRUPT TASK PRIORITY
TP
Operation R R R R R/W
Reset $00 $00 $00 $0 $F