Motorola MVME2300 Series - Manual (Page 144)

2-74 Computer Group Literature Center Web Site
Raven PCI Bridge ASIC
2
Global Configuration Register
R Reset Controller. Writing a 1 to this bit forces the
controller logic to be reset. The bit is cleared
automatically when the reset sequence is complete. While
this bit is set, the values of all other register are undefined.
M Cascade Mode. Allows cascading of an external 8259
pair connected to the first interrupt source input pin (0).
This bit will always be set to 1, indicating mixed mode. In
mixed mode, 8259 interrupts are delivered using the
priority and distribution mechanism of the RavenMPIC.
The Vector/Priority and Destination registers for interrupt
source 0 are used to control the delivery mode for all
8259-generated interrupt sources.
2Raven PCI Bridge ASIC
0Raven Interrupt Controller
Offset $01020
Bit 3
1 3
0 2
9 2
8 2
7 2
6 2
5 2
4 2
3 2
2 2
1 2
0 1
9 1
8 1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 9 8 7 6 5 4 3 2 1 0
Name GLOBAL CONFIGURATION
RESE
T
M
Operation
C R R/W
R R R R
Reset
0 0 0
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