FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 73)

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CHAPTER 3 CPU
3.7.2 Sleep Mode
This section describes the operations of sleep mode.
■ Operation of sleep mode
●
Entering sleep mode
Sleep mode stops the CPU operating clock. The CPU stops while maintaining all register contents, RAM
contents, and pin states at their values immediately prior to entering sleep mode. However, peripheral
functions except the watchdog timer continue to operate.
Writing "1" to the sleep bit in the standby control register (STBC: SLP) puts the CPU to sleep mode. If an
interrupt request is generated when "1" is written to the SLP bit, the write to the bit is ignored, and the CPU
continues the instruction execution without entering sleep mode. (The CPU does not go to sleep mode even
after completion of the interrupt processing.)
●
Wake-up from sleep mode
A reset or an interrupt from a peripheral function wakes up the CPU from sleep mode.
There is no oscillation stabilization delay period.
The reset operation also initializes the pin states.
If an interrupt request with an interrupt level higher than "11
B
" occurs from a peripheral function or an
external interrupt circuit during sleep mode, the CPU wakes up from sleep mode, regardless of the interrupt
enable flag (CCR: I) and interrupt level bits (CCR: IL1 and IL0) in the CPU.
The normal interrupt operation is performed after wake-up from sleep mode. If the interrupt request is
accepted, the CPU executes interrupt processing. If the interrupt request is not accepted, the CPU continues
execution from the subsequent instruction following the instruction executed immediately before entering
sleep mode.