HP BL860C - Manual (Page 103)

Processor Installation Order
For a minimally loaded server blade, one IPF processor module must be installed in processor slot
0. Slot 0 is the slot closer to the server blade chassis. Install a processor of the same version into
processor slot 1 (if purchased).
Processor Module Behaviors
All physical processors become functional after server power is applied. Each processor is in a
race to fetch their instructions from their processor instruction and data caches to complete early
self test and rendezvous.
It is the processor cache controller logic that issues cache line fetches from PDH/physical shared
memory, when a requested cache line is not within its instruction or data cache. Cache line fetches
are transferred over the McKinley bus, between processors and PDH/physical shared memory.
Local machine check abort (MCA) events cause one IPF processor module to fail, while the other
IPF processor module continues operating. Double-bit data cache errors in any physical processor
core causes a Global MCA event, that causes all IPF processor modules to fail and reboot the
operating system.
Customer Messaging Policy
No diagnostic messages are reported for single-bit errors, that are corrected in both instruction
and data caches, during corrected machine check (CMC) events to any physical processor core.
Diagnostic messages are reported for CMC events, when thresholds are exceeded for single-bit
errors; fatal processor errors cause global/local MCA events.
Troubleshooting Blade Memory
The memory controller logic in the zx1 chip supports two physical ranks, that hold 2 memory
DIMMs each.
Memory DIMMs installed in groups of two are known as a pair, and must be the same size and
configuration.
Memory DIMM Installation Order
For a minimally loaded server, two equal-size memory DIMMs must be installed into rank 0 slots
0A and 0B. The next two DIMMs are loaded into rank 1 slots 1A and 1B, and so forth.
Memory Subsystem Behaviors
All server blades with zx1 chips provide error detection and correction of all memory DIMM
single-bit errors, and error detection of most multibit errors within a 128 byte cache line.
The zx1 chip provides memory DIMM error correction for up to 4 bytes of a 128 byte cache line,
during cache line misses initiated by processor cache controllers, and by Direct Memory Access
(DMA) operations, initiated by I/O devices. This feature is called chip sparing, as 1 of 72 total
DRAMs in any memory pair can fail without any loss of server blade performance.
Customer Messaging Policy
PDT logs for all double bit errors are permanent; single bit errors are initially logged as transient
errors. If the server logs 2 single bit errors within 24 hours, it upgrades them to permanent status
in the PDT.
Troubleshooting Blade SBA
Each server blade’s system bus adapter (SBA) supports core I/O, SAS, LAN, and FibreChannel
functions. The System Bus Adapter (SBA) logic within the zx1 chip of a server blade uses 6 of 8
Troubleshooting Processors/Memory/SBA 103