Artesyn MITX-CORE-820 Installation and Use (July 2014) - Manual (Page 114)

Firmware
MITX-CORE-820 Installation and Use (6806800M10H) 114
/*
Time base is 1mS.
A --> "PORT PIN" of power sequence
B --> Active "HIGH" or "LOW"
C --> Delay time to next step.
D --> Next sequence. The terminated signature of the sequence is
"0x7F".
E --> Direction "OUTPUT" or "INPUT"
*/
const PWRSEQ_DESCRIPTOR PwrOnSeq_Table[] =
{
/* A B C D E */
{PORT_PIN(4, 0) | HIGH, 01, 0x01 | OUTPUT}, /* 0 - SB_ENABLE */
{PORT_PIN(0, 6) | HIGH, 20, 0x02 | INPUT}, /* 1 - SB_PWROK */
{PORT_PIN(4, 2) | HIGH, 20, 0x03 | OUTPUT}, /* 2 - RSMRST */
{PORT_PIN(3, 3) | LOW, 01, 0x0A | OUTPUT}, /* 3 - PWRBTN_SB */
{PORT_PIN(4, 7) | HIGH, 01, 0x7F | OUTPUT}, /* 4 - HW_PWRGD */
{PORT_PIN(0, 7) | HIGH, 00, 0x00 | INPUT }, /* 5 - SLP_S4 */
{PORT_PIN(5, 0) | HIGH, 100, 0x04 | OUTPUT}, /* 6 - CPU_VR_ON */
{PORT_PIN(3, 0) | HIGH, 120, 0x06 | INPUT }, /* 7 - ALLPWROK */
{UNUSED_PIN | LOW, 00, 0x00 | OUTPUT}, /* 8 - */
{UNUSED_PIN | LOW, 00, 0x00 | OUTPUT}, /* 9 - */
{PORT_PIN(1, 0) | HIGH, 01, 0x0B | INPUT }, /* A - SLP_S3 */
{PORT_PIN(4, 4) | HIGH, 01, 0x0C | OUTPUT}, /* B - SUSON */
{PORT_PIN(4, 5) | HIGH, 01, 0x07 | OUTPUT}, /* C - MAINON */
{UNUSED_PIN | LOW, 00, 0x00 | INPUT }, /* D - */
{UNUSED_PIN | LOW, 00, 0x00 | INPUT }, /* E - */
{UNUSED_PIN | LOW, 00, 0x00 | INPUT } /* F - */