5 kbc address to host processor, 6 ec i/o port, 1 ec status register – Artesyn MITX-CORE-820 Installation and Use (July 2014) User Manual
Page 106: 5 kbc address to host processor 6.2.6 ec i/o port, Table 6-3, Table 6-4, Ec status i/o port register, Firmware
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Firmware
MITX-CORE-820 Installation and Use (6806800M10H)
106
6.2.5
KBC Address to Host Processor
The legacy settings of the keyboard and mouse addresses are 60h and 64h for the
status/command and data registers.
This table shows the register mapping to the host processor I/O space. For simplicity, the host
interface module specification refers to the legacy addresses.
6.2.6
EC I/O Port
The EC standard commands as described in ACPI 2.0 specifications are directly processed by
the hardware logic. The data and command/status ports are set by default to 62h and 66h
respectively and can be optionally mapped to other I/O address.
6.2.6.1
EC Status Register
The following table shows the EC status I/O Port Register.
Table 6-3 Mapping of Host Interface Registers to the Host Processor
Port
Legacy
Address
Internal Chip Select
Type
Register Name
Keyboard and
Mouse
60h
Keyboard/Mouse Data
Write
Data
64h
Keyboard/mouse Command
Write
Command
60h
Keyboard/Mouse Data
Read
Data
64h
Keyboard/Mouse Command
Read
Status
Table 6-4 EC Status I/O Port Register
Status Bit
Name
Description
7
Reserved
6
Reserved
5
SCI
1: Indicates if there are more SCI event or events in the SCI
queue. Upon detecting this bit being set, the system should
query the SCI event queue to obtain the SCI ID number.
Receiving and completing the EC standard commands will not
cause the SCI bit to be set.