Artesyn MITX-CORE-820 Installation and Use (July 2014) - Manual (Page 102)

Firmware
MITX-CORE-820 Installation and Use (6806800M10H) 102
6.2 System BIOS Porting
6.2.1 Host Configuration Address
The host processor accesses the NPCE791x keyboard/mouse host interface and registers at
two addresses in the host address domain. These addresses are defined by two internal chip
select specified in the NPCE791x host configuration registers.
6.2.2 Index-Data Register Pair
The core can set the address of the Super I/O configuration index/data register using HCBAL
and HCBAH, which are byte-wide read/write register. HCBAL holds the least significant byte of
a host motherboard PnP initial configuration address; while HCBAH holds the most significant
byte. HCBAL and HCBAH registers are set to their default values by power-up reset and input
reset. HCBAH is set to 00h, HCBAL is set to 4Eh to Super I/O configuration index/data address
of 4E/4Fh. However, the HCBAL and HCBAH registers can be modified by a special process,
please refer to NPCE791x datasheet.
6.2.3 Blanked Logical Device Register Structure
Each functional block is associated with a logical device number (LDN). The configuration
registers are grouped in banks, with each bank holding the standard configuration registers of
the corresponding logical device.
This table shows the LDN values of the NPCE791x functional blocks. Any value not listed is set
as reserved.
Table 6-1 LDN Values
LDN Functional Block
03h Serial Port 1
04h Mobile System Wake-Up Control
05h KBC - Mouse Interface
06h KBC - Keyboard interface
0Fh Shared Memory