Artesyn ATCA-MF106 Installation and Use (September 2014) - Manual (Page 45)

ATCA-MF106 Hardware
ATCA-MF106 Installation and Use (6806800M62B) 45
2.2.2 Redundancy Interfaces
The ATCA-MF106 uses a private, redundant, high-speed, full duplex serial connection for
heartbeating and data replication between the two shelf managers.
The redundancy interface is routed to the backplane via differential line LVDS transceivers. The
physical interface of both channels is compliant with the PICMG 3.0 R3.0 (AdvancedTCA)
specification for the update interface.
Each of the serial inputs of the redundancy interface triggers an interrupt to the PowerQUICC
when the other shelf manager:
 initiates a break-in condition on the serial line
 experiences a power failure
 goes in the reset state
 is extracted
2.2.3 Block Transfer Interface
The payload CPU is connected to the ShMC via a parallel interface with interrupt support called
block transfer interface, implemented in a FPGA.
The block transfer (BT) interface is compliant with IPMI specification v1.5.
2.3 Shelf Management Controller
The ShMC part is derived from Artesyn Embedded Technologies's IPMC building block and
consists of two coupled microcontrollers:
 IPMC Master Controller (IMC) based on an Atmega 128
 IPMC Slave Controller (ISC), based on an Atmega 8
2.3.1 IPMB0 Interface
IPMB0-A is connected to the I
2
C controller of the IMC, IPMB0-B to the I
2
C controller of the ISC
of the ShMC. Both microcontrollers have their own I
2
C controller and handle message
transmission and reception independently, including bus error handling and bus arbitration.