Development board block diagram, Handling the board – Altera Arria V SoC Development Board User Manual
Page 8
1–4
Chapter 1: Overview
Development Board Block Diagram
July 2014
Altera Corporation
Reference Manual
Development Board Block Diagram
shows a block diagram of the Arria V SoC development board.
Handling the Board
When handling the board, it is important to observe the following static discharge
precaution:
c
Without proper anti-static handling, the board can be damaged. Therefore, use
anti-static handling precautions when touching the board.
Figure 1–1. Arria V SoC Development Board Block Diagram
DDR3 1GB
533 MHz (x32)
DDR3 1GB
533 MHz (x32)
Clock
Cleaner
Jitter
Clean Up
Buttons
Switches
LEDs
Buttons
Switches
LEDs
CSEL
BSEL
HMC
HMC
HMC
10/100 Dual
Ethernet PHY
SFP+ x2
FMC x2
MAX V
CPLD
PCIe Gen2
x4
Parallel
Configuration
Flash
DDR3 1GB
533 MHz + ECC
QSPI Flash
256 MB
Micro SD Card
USB 2.0
OTG PHY
10/100/1000
Ethernet PHY
UART to USB
UART to USB
I
2
C
Power
Management
Measurement
Serial
EPROM
RTC
2x16
Character
LCD
MAC Address
Storage
FPGA
HPS
JTAG
JTAG
USB-Blaster II
USB 2.0
MAX II
CPLD
Mictor
Connector
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)