Altera Arria V SoC Development Board - Manual (Page 46)

2–38 Chapter 2: Board Components
Components and Interfaces
Arria V SoC Development Board July 2014 Altera Corporation
Reference Manual
I 2 C Interface
The HPS system has one I 2 C interface for communicating with the on-board and
external components using a data rate of 400 Kbps.
Table 2–26 lists the I 2 C interface address map.
18 SFPA_TX_P AD3 PCML Transmitter data
7 SFPA_RATESEL0 AU6 3.3-V LVTTL Rate select
9 SFPA_RATESEL1 AL8 3.3-V LVTTL Rate select
SFP+ Port B (J43)
6 SFPB_MOD0_PRSNTn AP8 3.3-V LVTTL Module present indicator
8 SFPB_LOS AG21 3.3-V LVTTL Signal present indicator
2 SFPB_TXFAULT AK20 3.3-V LVTTL Transmitter fault indicator
12 SFPB_RX_N W2 PCML Receiver data
13 SFPB_RX_P W1 PCML Receiver data
5 SFPB_MOD1_SCL AN8 3.3-V LVTTL Serial 2-wire clock
4 SFPB_MOD1_SDA AJ7 3.3-V LVTTL Serial 2-wire data
3 SFPB_TXDISABLE AT6 3.3-V LVTTL Drive low to disable transmitter
19 SFPB_TX_N Y4 PCML Rate select
18 SFPB_TX_P Y3 PCML Rate select
7 SFPB_RATESEL0 AK8 3.3-V LVTTL Reserved
9 SFPB_RATESEL1 AN7 3.3-V LVTTL Reserved
Table 2–25. SFP+ Ports Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Board
Reference
Schematic
Signal Name
Arria V SoC
Pin Number
I/O Standard Description
Table 2–26. I 2 C interface address map
Address Device
0x68 Real-time clock
0x50 LCD
0x51 EEPROM
0x5C HPS power monitor
0x5E FPGA power monitor 1
0x62 FPGA power monitor 2
0x55 Si571 programmable oscillator
0x66 Si570 programmable oscillator
0x70 Si5338 quad-programmable clock