Altera Arria V SoC Development Board User Manual
Page 16
2–8
Chapter 2: Board Components
MAX V CPLD 5M2210 System Controller
July 2014
Altera Corporation
Reference Manual
L14
FM_D13
1.8-V
FM data bus
N16
FM_D14
1.8-V
FM data bus
M13
FM_D15
1.8-V
FM data bus
M3
FMC_C2M_PG
2.5-V
FMC port A power good output
N2
FMCB_C2M_PG
2.5-V
FMC port B power good output
K1
FPGA_CONF_DONE
2.5-V
FPGA configuration done LED
D3
FPGA_CONFIG_D0
2.5-V
FPGA configuration data
C2
FPGA_CONFIG_D1
2.5-V
FPGA configuration data
C3
FPGA_CONFIG_D2
2.5-V
FPGA configuration data
E3
FPGA_CONFIG_D3
2.5-V
FPGA configuration data
D2
FPGA_CONFIG_D4
2.5-V
FPGA configuration data
E4
FPGA_CONFIG_D5
2.5-V
FPGA configuration data
D1
FPGA_CONFIG_D6
2.5-V
FPGA configuration data
E5
FPGA_CONFIG_D7
2.5-V
FPGA configuration data
F3
FPGA_CONFIG_D8
2.5-V
FPGA configuration data
E1
FPGA_CONFIG_D9
2.5-V
FPGA configuration data
F4
FPGA_CONFIG_D10
2.5-V
FPGA configuration data
F2
FPGA_CONFIG_D11
2.5-V
FPGA configuration data
F1
FPGA_CONFIG_D12
2.5-V
FPGA configuration data
F6
FPGA_CONFIG_D13
2.5-V
FPGA configuration data
G2
FPGA_CONFIG_D14
2.5-V
FPGA configuration data
G3
FPGA_CONFIG_D15
2.5-V
FPGA configuration data
N3
FPGA_CVP_CONFDONE
2.5-V
FPGA Configuration via Protocol (CvP) done
J3
FPGA_DCLK
2.5-V
FPGA configuration clock
N1
FPGA_NCONFIG
2.5-V
FPGA configuration active
J4
FPGA_NSTATUS
2.5-V
FPGA configuration ready
H1
FPGA_PR_DONE
2.5-V
FPGA partial reconfiguration done
P2
FPGA_PR_ERROR
2.5-V
FPGA partial reconfiguration error
E2
FPGA_PR_READY
2.5-V
FPGA partial reconfiguration ready
F5
FPGA_PR_REQUEST
2.5-V
FPGA partial reconfiguration request
B11
HPS_RESETN
2.5-V
HPS reset push button
M1
I2C_SCL_MAX
2.5-V
Programmable oscillator I
2
C clock
M2
I2C_SDA_MAX
2.5-V
Programmable oscillator I
2
C data
L6
JTAG_MAX_TDI
2.5-V
JTAG chain data in
M5
JTAG_MAX_TDO
2.5-V
JTAG chain data out
N4
JTAG_MAX_TMS
2.5-V
JTAG chain mode
P3
JTAG_MUX_TCK
2.5-V
JTAG chain clock
P11
M570_CLOCK
1.5-V
25-MHz clock to on-board USB-Blaster II for sending
FACTORY command
Table 2–3. MAX V CPLD System Controller Device Pin-Out (Part 3 of 5)
Board
Reference (U27)
Schematic Signal Name
I/O Standard
Description