Altera Arria V SoC Development Board - Manual (Page 61)

Chapter 2: Board Components 2–53
Power Supply
July 2014 Altera Corporation Arria V SoC Development Board
Reference Manual
I 2 C EEPROM
This board includes a 32 Kb EEPROM device. This device has a 2-wire I 2 C serial
interface bus and is organized as four blocks of 4K x 8-bit memory. The main function
of the device is for EtherCAT IP usage, but it can be used for other storage purposes as
well.
Table 2–33 lists the I 2 C EEPROM pin assignments, signal names, and functions. The
signal names and types are relative to the Arria V SoC in terms of I/O setting and
direction.
Power Supply
You can power up the development board from a laptop-style DC power input or
through the DC auxiliary connector. The Arria V SoC is designed in such way that the
power rails for the HPS and FPGA are independent, allowing power down for the
FPGA side when the HPS side is running. This eliminates power consumption on the
FPGA part when not in use.
Table 2–34 lists the maximum allowed draws of the power input.
An on-board multi-channel analog-to-digital converter (ADC) measures the current
for several specific board rails.
8 SD_DAT1 N16 3.3-V Data bus
1 SD_DAT2 J16 3.3-V Data bus
2 SD_CD_DAT3 M16 3.3-V Control or data bus
3 SD_CMD D16 3.3-V Control
Table 2–32. Micro SD Flash Memory Interface Schematic Signal Names and Functions (Part 2 of 2)
Board
Reference (J5)
Schematic Signal
Name
Arria V SoC Pin
Number
I/O Standard Description
Table 2–33. I 2 C EEPROM Schematic Signal Names and Functions
Board
Reference (U34)
Schematic Signal
Name
Arria V SoC Pin
Number
I/O Standard Description
6 I2C_SCL_HPS L13 3.3-V Management serial clock
5 I2C_SDA_HPS C13 3.3-V Management serial data
Table 2–34. Power Input Maximum Allowed Draws
Source Voltage (V) Wattage (W)
Laptop Supply—DC input
16.0 300
20.0 200
DC auxiliary connector 12.0 200