Altera Arria V SoC Development Board - Manual (Page 5)

July 2014 Altera Corporation Arria V SoC Development Board
Reference Manual
1. Overview
This document describes the hardware features of the Arria ® V SoC development
board, including the detailed pin-out and component reference information required
to create custom FPGA designs that interface with all components of the board.
General Description
The Arria V SoC development board provides a hardware platform for developing
and prototyping low-power, high-performance, and logic-intensive designs using
Altera’s Arria V SoC. The board provides a wide range of peripherals and memory
interfaces to facilitate the development of Arria V SoC designs.
f For more information about the Arria V device family, refer to the Arria V Device
Handbook .
Board Component Blocks
The development board features the following major component blocks:
■ One Arria V SoC (5ASTFD5K3F40I3) in a 1517-pin FBGA package
■ FPGA configuration circuitry
■ Active Serial (AS) x1 or x4 configuration (EPCQ256SI16N)
■ MAX ® V CPLD (5M2210ZF256) in a 256-pin FBGA package as the System
Controller
■ Flash fast passive parallel (FPP) configuration
■ MAX II CPLD (EPM570GF100) as part of the on-board USB-Blaster TM II for use
with the Quartus ® II Programmer
■ Clocking circuitry
■ Si570, Si571, and Si5338 programmable oscillators
■ 50-MHz, 66-MHz, 100-MHz, 125-MHz programmable oscillators
■ SMA input (LVCMOS)