Altera Arria V SoC Development Board - Manual (Page 33)

Chapter 2: Board Components 2–25
Components and Interfaces
July 2014 Altera Corporation Arria V SoC Development Board
Reference Manual
10/100/1000 Ethernet (HPS)
The development board supports an RJ-45 10/100/1000 base-T Ethernet using an
external Micrel KSZ9021RN PHY and the HPS EMAC function from the Altera
Triple-Speed Ethernet MegaCore MAC function. The PHY-to-MAC interface employs
RGMII connection using four data lines at 250 Mbps each for a connection speed of
1 Gbps.
The Micrel KSZ9021RN PHY uses 2.5-V or 3.3-V power rails. The PHY interfaces to an
RJ-45 model with internal magnetics that can be used for driving copper lines with
Ethernet traffic.
Figure 2–7 shows the RGMII interface between the HPS (MAC) and Micrel
KSZ9021RN PHY.
Table 2–17 lists the HPS Ethernet PHY interface pin assignments.
Figure 2–7. RGMII Interface between HPS (MAC) and PHY
RGMII
Mac
Single-Port RGMII
Micrel KSZ9021RN
RJ-45
Table 2–17. Ethernet PHY (HPS) Pin Assignments, Signal Names and Functions (Part 1 of 2)
Board
Reference (U7)
Schematic Signal Name
Arria V SoC Pin
Number
I/O Standard Description
41 CLK125_NDO_LED_MODE — — Clock out 125-MHz LED mode
24 ENET_HPS_GTX_CLK D19 3.3-V CMOS 125-MHz RGMII transmit clock
38 ENET_HPS_INTN A18 3.3-V CMOS Management bus interrupt
17 ENET_HPS_LED1_LINK — 3.3-V CMOS Receive data active LED
15 ENET_HPS_LED2_LINK — 3.3-V CMOS Transmit data active LED
36 ENET_HPS_MDC L18 3.3-V CMOS Management bus data clock
37 ENET_HPS_MDIO J18 3.3-V CMOS Management bus data
42 ENET_HPS_RESETN — 3.3-V CMOS Device reset
48 ENET_HPS_RSET — 3.3-V CMOS Device interrupt
35 ENET_HPS_RX_CLK G21 3.3-V CMOS RGMII receive clock
33 ENET_HPS_RX_DV H19 3.3-V CMOS RGMII receive data valid
32 ENET_HPS_RXD0 E19 3.3-V CMOS RGMII receive data bus
31 ENET_HPS_RXD1 M17 3.3-V CMOS RGMII receive data bus
28 ENET_HPS_RXD2 G20 3.3-V CMOS RGMII receive data bus
27 ENET_HPS_RXD3 G19 3.3-V CMOS RGMII receive data bus
25 ENET_HPS_TX_EN N18 3.3-V CMOS RGMII transmit enable
19 ENET_HPS_TXD0 H18 3.3-V CMOS RGMII transmit data bus
20 ENET_HPS_TXD1 F19 3.3-V CMOS RGMII transmit data bus