Altera Arria V SoC Development Board - Manual (Page 32)

2–24 Chapter 2: Board Components
Components and Interfaces
Arria V SoC Development Board July 2014 Altera Corporation
Reference Manual
Table 2–16. PCI Express Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (J42)
Schematic Signal
Name
I/O Standard
Arria V SoC Device Pin
Number
Description
A11 PCIE_PERSTN LVTTL AK6 Reset
B17 PCIE_PRSNT2N_X1 LVTTL AC22 Presence detect DIP switch
B31 PCIE_PRSNT2N_X4 LVTTL AD21 Presence detect DIP switch
A14 PCIE_REFCLK_SYN_N HCSL AF7 Motherboard reference clock
A13 PCIE_REFCLK_SYN_P HCSL AF8 Motherboard reference clock
B5 PCIE_SMCLK LVTTL AG20 SMB clock
B6 PCIE_SMDAT LVTTL AG23 SMB data
B11 PCIE_WAKEN LVTTL AL6 Wake signal
A17 PCIE_RX_N0 1.5-V PCML AU2 Receive bus
A22 PCIE_RX_N1 1.5-V PCML AR2 Receive bus
A26 PCIE_RX_N2 1.5-V PCML AN2 Receive bus
A30 PCIE_RX_N3 1.5-V PCML AL2 Receive bus
A16 PCIE_RX_P0 1.5-V PCML AU1 Receive bus
A21 PCIE_RX_P1 1.5-V PCML AR1 Receive bus
A25 PCIE_RX_P2 1.5-V PCML AN1 Receive bus
A29 PCIE_RX_P3 1.5-V PCML AL1 Receive bus
B15 PCIE_TX_N0 1.5-V PCML AT4 Transmit bus
B20 PCIE_TX_N1 1.5-V PCML AP4 Transmit bus
B24 PCIE_TX_N2 1.5-V PCML AM4 Transmit bus
B28 PCIE_TX_N3 1.5-V PCML AK4 Transmit bus
B14 PCIE_TX_P0 1.5-V PCML AT3 Transmit bus
B19 PCIE_TX_P1 1.5-V PCML AP3 Transmit bus
B23 PCIE_TX_P2 1.5-V PCML AM3 Transmit bus
B27 PCIE_TX_P3 1.5-V PCML AK3 Transmit bus