Altera Arria V SoC Development Board User Manual

Page 49

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Chapter 2: Board Components

2–41

Memory

July 2014

Altera Corporation

Arria V SoC Development Board

Reference Manual

C7

DDR3A_DQS_P3

AU26

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 3

B7

DDR3A_DQS_N3

AT26

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 3

K1

DDR3A_ODT

AM31

1.5-V SSTL Class I

On-die termination enable

J3

DDR3A_RASN

AN31

1.5-V SSTL Class I

Row address select

T2

DDR3A_RESETN

AB29

1.5-V SSTL Class I

Reset

L3

DDR3A_WEN

AW33

1.5-V SSTL Class I

Write enable

L8

DDR3A_ZQ1

—

1.5-V SSTL Class I

ZQ impedance calibration

DDR3 x16 (U29)

N3

DDR3A_A0

AU29

1.5-V SSTL Class I

Address bus

P7

DDR3A_A1

AT29

1.5-V SSTL Class I

Address bus

P3

DDR3A_A2

AV30

1.5-V SSTL Class I

Address bus

N2

DDR3A_A3

AU30

1.5-V SSTL Class I

Address bus

P8

DDR3A_A4

AT30

1.5-V SSTL Class I

Address bus

P2

DDR3A_A5

AR30

1.5-V SSTL Class I

Address bus

R8

DDR3A_A6

AL30

1.5-V SSTL Class I

Address bus

R2

DDR3A_A7

AK30

1.5-V SSTL Class I

Address bus

T8

DDR3A_A8

AW31

1.5-V SSTL Class I

Address bus

R3

DDR3A_A9

AW30

1.5-V SSTL Class I

Address bus

L7

DDR3A_A10

AV31

1.5-V SSTL Class I

Address bus

R7

DDR3A_A11

AU31

1.5-V SSTL Class I

Address bus

N7

DDR3A_A12

AH30

1.5-V SSTL Class I

Address bus

T3

DDR3A_A13

AG30

1.5-V SSTL Class I

Address bus

T7

DDR3A_A14

AE29

1.5-V SSTL Class I

Address bus

M2

DDR3A_BA0

AT31

1.5-V SSTL Class I

Bank address bus

N8

DDR3A_BA1

AR31

1.5-V SSTL Class I

Bank address bus

M3

DDR3A_BA2

AP31

1.5-V SSTL Class I

Bank address bus

K3

DDR3A_CASN

AW32

1.5-V SSTL Class I

Row address select

K9

DDR3A_CKE

AP30

1.5-V SSTL Class I

Column address select

J7

DDR3A_CLK_P

AP29

1.5-V SSTL Class I

Differential output clock

K7

DDR3A_CLK_N

AN29

1.5-V SSTL Class I

Differential output clock

L2

DDR3A_CSN

AP32

1.5-V SSTL Class I

Chip select

E7

DDR3A_DM0

AF27

1.5-V SSTL Class I

Write mask byte lane

D3

DDR3A_DM1

AK25

1.5-V SSTL Class I

Write mask byte lane

H3

DDR3A_DQ0

AH25

1.5-V SSTL Class I

Data bus

F8

DDR3A_DQ1

AG25

1.5-V SSTL Class I

Data bus

G2

DDR3A_DQ2

AE26

1.5-V SSTL Class I

Data bus

H8

DDR3A_DQ3

AH26

1.5-V SSTL Class I

Data bus

Table 2–27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 7)

Board

Reference

Schematic

Signal Name

Arria V SoC Pin

Number

I/O Standard

Description