Altera Arria V SoC Development Board - Manual (Page 25)

Chapter 2: Board Components 2–17
Setup Elements
July 2014 Altera Corporation Arria V SoC Development Board
Reference Manual
JTAG Chain Control DIP Switch
The JTAG chain control DIP switch (SW4) either removes or includes devices in the
active JTAG chain.
Table 2–8 lists the switch controls and its descriptions.
FPGA Configuration Mode DIP Switch
The FPGA configuration mode DIP switch (SW3) defines the mode to use to configure
the FPGA.
Table 2–9 lists the switch controls and its descriptions. All switches at the
ON position will select the default FPP x16 mode.
Table 2–8. JTAG Chain Control DIP Switch
Switch
Schematic Signal
Name
Description
1 HPS_JTAG_EN
ON: Do not Include HPS in the JTAG chain.
OFF: Include HPS in the JTAG chain.
2 FPGA_JTAG_EN
ON: Do not Include the FPGA in the JTAG chain.
OFF: Include the FPGA in the JTAG chain.
3 FMC_JTAG_EN
ON: Do not include the FMCA connector in the JTAG chain.
OFF: Include the FMCA connector in the JTAG chain.
4 MAX_JTAG_EN
ON: Do not include the MAX V system controller in the JTAG chain.
OFF: Include the MAX V system controller in the JTAG chain.
Table 2–9. FPGA Configuration Mode DIP Switch
Switch
Schematic Signal
Name
Description
1 MSEL0
ON: Select logic 0
OFF: Select logic 1
2 MSEL1
ON: Select logic 0
OFF: Select logic 1
3 MSEL2
ON: Select logic 0
OFF: Select logic 1
4 MSEL3
ON: Select logic 0
OFF: Select logic 1
5 MSEL4
ON: Select logic 0
OFF: Select logic 1