Altera Arria V SoC Development Board - Manual (Page 56)

2–48 Chapter 2: Board Components
Memory
Arria V SoC Development Board July 2014 Altera Corporation
Reference Manual
C2 DDR3_HPS_DQ28 G2 1.5-V SSTL Class I Data bus
A2 DDR3_HPS_DQ29 F2 1.5-V SSTL Class I Data bus
B8 DDR3_HPS_DQ30 M3 1.5-V SSTL Class I Data bus
D7 DDR3_HPS_DQ31 E1 1.5-V SSTL Class I Data bus
F3 DDR3_HPS_DQS_P2 G4
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 1
G3 DDR3_HPS_DQS_N2 H4
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 0
C7 DDR3_HPS_DQS_P3 C2
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 1
B7 DDR3_HPS_DQS_N3 D2
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 0
K1 DDR3_HPS_ODT H7 1.5-V SSTL Class I On-die termination enable
J3 DDR3_HPS_RASN G8 1.5-V SSTL Class I Row address select
T2 DDR3_HPS_RESETN E3 1.5-V SSTL Class I Reset
L3 DDR3_HPS_WEN J8 1.5-V SSTL Class I Write enable
L8 DDR3_HPS_ZQ2 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3 x16 (U38)
N3 DDR3_HPS_A0 N9 1.5-V SSTL Class I Address bus
P7 DDR3_HPS_A1 M9 1.5-V SSTL Class I Address bus
P3 DDR3_HPS_A2 N10 1.5-V SSTL Class I Address bus
N2 DDR3_HPS_A3 M10 1.5-V SSTL Class I Address bus
P8 DDR3_HPS_A4 A8 1.5-V SSTL Class I Address bus
P2 DDR3_HPS_A5 B7 1.5-V SSTL Class I Address bus
R8 DDR3_HPS_A6 B9 1.5-V SSTL Class I Address bus
R2 DDR3_HPS_A7 A9 1.5-V SSTL Class I Address bus
T8 DDR3_HPS_A8 D9 1.5-V SSTL Class I Address bus
R3 DDR3_HPS_A9 C10 1.5-V SSTL Class I Address bus
L7 DDR3_HPS_A10 K7 1.5-V SSTL Class I Address bus
R7 DDR3_HPS_A11 J7 1.5-V SSTL Class I Address bus
N7 DDR3_HPS_A12 F9 1.5-V SSTL Class I Address bus
T3 DDR3_HPS_A13 E9 1.5-V SSTL Class I Address bus
T7 DDR3_HPS_A14 D11 1.5-V SSTL Class I Address bus
M2 DDR3_HPS_BA0 L7 1.5-V SSTL Class I Bank address bus
N8 DDR3_HPS_BA1 C9 1.5-V SSTL Class I Bank address bus
M3 DDR3_HPS_BA2 D8 1.5-V SSTL Class I Bank address bus
K3 DDR3_HPS_CASN G9 1.5-V SSTL Class I Row address select
K9 DDR3_HPS_CKE R8 1.5-V SSTL Class I Column address select
J7 DDR3_HPS_CLK_P A11 1.5-V SSTL Class I Differential output clock
Table 2–28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5)
Board
Reference
Schematic
Signal Name
Arria V SoC Pin
Number
I/O Standard Description