Altera Arria V SoC Development Board User Manual

Page 48

background image

2–40

Chapter 2: Board Components

Memory

Arria V SoC Development Board

July 2014

Altera Corporation

Reference Manual

T8

DDR3A_A8

AW31

1.5-V SSTL Class I

Address bus

R3

DDR3A_A9

AW30

1.5-V SSTL Class I

Address bus

L7

DDR3A_A10

AV31

1.5-V SSTL Class I

Address bus

R7

DDR3A_A11

AU31

1.5-V SSTL Class I

Address bus

N7

DDR3A_A12

AH30

1.5-V SSTL Class I

Address bus

T3

DDR3A_A13

AG30

1.5-V SSTL Class I

Address bus

T7

DDR3A_A14

AE29

1.5-V SSTL Class I

Address bus

M2

DDR3A_BA0

AT31

1.5-V SSTL Class I

Bank address bus

N8

DDR3A_BA1

AR31

1.5-V SSTL Class I

Bank address bus

M3

DDR3A_BA2

AP31

1.5-V SSTL Class I

Bank address bus

K3

DDR3A_CASN

AW32

1.5-V SSTL Class I

Row address select

K9

DDR3A_CKE

AP30

1.5-V SSTL Class I

Column address select

J7

DDR3A_CLK_P

AP29

Differential 1.5-V

SSTL Class I

Differential output clock

K7

DDR3A_CLK_N

AN29

Differential 1.5-V

SSTL Class I

Differential output clock

L2

DDR3A_CSN

AP32

1.5-V SSTL Class I

Chip select

E7

DDR3A_DM2

AF27

1.5-V SSTL Class I

Write mask byte lane

D3

DDR3A_DM3

AK25

1.5-V SSTL Class I

Write mask byte lane

F7

DDR3A_DQ16

AH25

1.5-V SSTL Class I

Data bus

E3

DDR3A_DQ17

AG25

1.5-V SSTL Class I

Data bus

F8

DDR3A_DQ18

AE26

1.5-V SSTL Class I

Data bus

H8

DDR3A_DQ19

AH26

1.5-V SSTL Class I

Data bus

H7

DDR3A_DQ20

AG26

1.5-V SSTL Class I

Data bus

F2

DDR3A_DQ21

AD25

1.5-V SSTL Class I

Data bus

G2

DDR3A_DQ22

AC25

1.5-V SSTL Class I

Data bus

H3

DDR3A_DQ23

AB25

1.5-V SSTL Class I

Data bus

C2

DDR3A_DQ24

AV24

1.5-V SSTL Class I

Data bus

C3

DDR3A_DQ25

AV25

1.5-V SSTL Class I

Data bus

C8

DDR3A_DQ26

AL26

1.5-V SSTL Class I

Data bus

A3

DDR3A_DQ27

AW26

1.5-V SSTL Class I

Data bus

D7

DDR3A_DQ28

AW25

1.5-V SSTL Class I

Data bus

A2

DDR3A_DQ29

AT25

1.5-V SSTL Class I

Data bus

A7

DDR3A_DQ30

AN25

1.5-V SSTL Class I

Data bus

B8

DDR3A_DQ31

AM25

1.5-V SSTL Class I

Data bus

F3

DDR3A_DQS_P2

AF25

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 2

G3

DDR3A_DQS_N2

AE25

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 2

Table 2–27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 7)

Board

Reference

Schematic

Signal Name

Arria V SoC Pin

Number

I/O Standard

Description