Altera Stratix IV E FPGA Development Board User Manual
Page 7

Chapter 1: Overview
1–3
Board Component Blocks
May 2011
Altera Corporation
Stratix IV E FPGA Development Board Reference Manual
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General user I/O
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LEDs and displays
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Eight user LEDs
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One power on LED
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One configuration done LED
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Three HSMC LEDs per interface — one transmit (TX), one receive (RX) and
one presence detect (PSNTn)
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Factory LEDs (LOAD, FACTORY, ERROR, USER_1, and USER_2)
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Single quad seven-segment display
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128 x 64 graphics display
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16-character x 2-line LCD display
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Push-Button switches
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One CPU reset push-button switch
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One system reset push-button switch
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One user reset push-button switch
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One factory configuration push-button switch
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One reset configuration push-button switch
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Four general user push-button switches
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One 16-position rotary switch
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DIP switches
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One eight-position user DIP switch
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One eight-position MAX
II CPLD EPM2210 System Controller specific DIP
switch
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One four-position clock enable DIP switch
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Power supply
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14-V – 20-V DC input
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On-board power measurement circuitry
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20-W per HSMC interface
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Mechanical
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8.25” x 7” board
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Bench-top operation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)