Altera Stratix IV E FPGA Development Board - Manual (Page 56)

2–48 Chapter 2: Board Components
Memory
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
U11.A2 Address bus QDRII_A20
1.5-V HSTL Class I
E13
U11.C6 Address bus QDRII_A21 B14
U11.B7 Write byte select 0 QDRII_BWSN0 C11
U11.A5 Write byte select 1 QDRII_BWSN1 D11
U11.A1 Read clock N QDRII_CQ_N Differential 1.5-V
HSTL Class I
C4
U11.A11 Read clock P QDRII_CQ_P H11
U11.P10 Write data bit QDRII_D0
1.5-V HSTL Class I
A9
U11.N11 Write data bit QDRII_D1 B10
U11.M11 Write data bit QDRII_D2 B11
U11.K10 Write data bit QDRII_D3 A11
U11.J11 Write data bit QDRII_D4 E11
U11.G11 Write data bit QDRII_D5 A12
U11.E10 Write data bit QDRII_D6 C12
U11.D11 Write data bit QDRII_D7 D12
U11.C11 Write data bit QDRII_D8 D13
U11.B3 Write data bit QDRII_D9 L14
U11.C3 Write data bit QDRII_D10 K15
U11.D2 Write data bit QDRII_D11 K13
U11.F3 Write data bit QDRII_D12 K14
U11.G2 Write data bit QDRII_D13 G13
U11.J3 Write data bit QDRII_D14 D10
U11.L3 Write data bit QDRII_D15 F11
U11.M3 Write data bit QDRII_D16 F13
U11.N2 Write data bit QDRII_D17 G12
U11.H1 DLL enable QDRII_DOFFn K12
U11.A6 Write clock N QDRII_K_N Differential 1.5-V
HSTL Class I
H14
U11.B6 Write clock P QDRII_K_P J14
U11.R6 On-die termination QDRII_ODT
1.5-V HSTL Class I
C3
U11.P11 Read data bit QDRII_Q0 A3
U11.M10 Read data bit QDRII_Q1 B4
U11.L11 Read data bit QDRII_Q2 A4
U11.K11 Read data bit QDRII_Q3 A5
U11.J10 Read data bit QDRII_Q4 C6
U11.F11 Read data bit QDRII_Q5 F8
U11.E11 Read data bit QDRII_Q6 G9
U11.C10 Read data bit QDRII_Q7 F9
U11.B11 Read data bit QDRII_Q8 G10
U11.B2 Read data bit QDRII_Q9 J12
U11.D3 Read data bit QDRII_Q10 J11
Table 2–45. QDR II+ SRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board Reference Description
Schematic Signal Name
I/O Standard
Stratix IV E Device
Pin Number