Altera Stratix IV E FPGA Development Board - Manual (Page 15)

Chapter 2: Board Components 2–7
MAX II CPLD EPM2210 System Controller
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
MAX II CPLD EPM2210 System Controller
The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the
following purposes:
■ FPGA configuration from flash memory
■ Power consumption monitoring
■ Temperature monitoring
■ Fan control
■ Virtual JTAG interface for PC-based power and temperature GUI
■ Control registers for clocks
■ Control registers for remote system update
Figure 2–3 illustrates the MAX II CPLD EPM2210 System Controller's functionality
and external circuit connections as a block diagram.
Table 2–5 lists the I/O signals present on the MAX II CPLD EPM2210 System
Controller. The signal names and functions are relative to the MAX II device (U10).
Figure 2–3. MAX II CPLD EPM2210 System Controller Block Diagram
MAX1619
Controller
Information
Register
EMB
Blaster
MAX II Device
SLD-HUB
PFL
FSM BUS
Power
Measure
Results
Virtual-JTAG
PC
Temperature
Measure
Results
FPGA
LTC2418
Controller
FLASH
Decoder Encoder
GPIO
JTAG Control
SRAM
Control
Register
Fast Configuration
Downloader
Table 2–5. MAX II CPLD EPM2210 System Controller Device (U10) Pin-Out (Part 1 of 5)
Schematic Signal Name
I/O
Standard
EPM2210
Pin Number
Stratix IV E
Device
Pin Number
Other
Connections
Description
2.5V_FPGA_PG 2.5-V E9 — U41.7 FPGA 2.5-V power good monitor
2.5V_HSMC_PG 2.5-V A7 — U26.7 HSMC 2.5-V power good monitor