Altera Stratix IV E FPGA Development Board - Manual (Page 61)

Chapter 2: Board Components 2–53
Memory
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
Table 2–49 lists the SSRAM pin assignments, signal names, and functions.
Table 2–49. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)
Board
Reference
Description Schematic Signal
Name
I/O
Standard
Stratix IV E
Device
Pin Number
Other Connections
U3.R6 Address bus FSM_A2
2.5-V
G23 U10.T9, U2.B1
U3.P6 Address bus FSM_A3 F23 U10.R9, U2.C1
U3.A2 Address bus FSM_A4 D27 U10.P9, U2.D1
U3.A10 Address bus FSM_A5 D28 U10.T10, U2.D2
U3.B2 Address bus FSM_A6 F25 U10.P13, U2.A2
U3.B10 Address bus FSM_A7 F26 U10.R10, U2.C2
U3.N6 Address bus FSM_A8 G24 U10.M10, U2.A3
U3.P3 Address bus FSM_A9 F24 U10.T11, U2.B3
U3.P4 Address bus FSM_A10 E26 U10.N10, U2.C3
U3.P8 Address bus FSM_A11 D26 U10.R11, U2.D3
U3.P9 Address bus FSM_A12 A30 U10.P10, U2.C4
U3.P10 Address bus FSM_A13 A33 U10.T12, U2.A5
U3.P11 Address bus FSM_A14 B31 U10.M11, U2.B5
U3.R3 Address bus FSM_A15 A31 U10.R12, U2.C5
U3.R4 Address bus FSM_A16 B32 U10.N11, U2.D7
U3.R8 Address bus FSM_A17 A32 U10.T13, U2.D8
U3.R9 Address bus FSM_A18 M23 U10.P11, U2.A7
U3.R10 Address bus FSM_A19 L23 U10.R13, U2.B7
U3.R11 Address bus FSM_A20 B29 U10.M12, U2.C7
U3.B1 Address bus FSM_A21 C29 U10.R14, U2.C8
U3.A1 Address bus FSM_A22 C31 U10.N12, U2.A8
U3.B11 Address bus FSM_A23 D31 U10.T15, U2.G1
U3.C10 Address bus FSM_A24 F27 U10.P12, U2.H8
U3.P2 Address bus FSM_A25 D18 U10.E13, U2.B6
U3.J10 Data bus FSM_D0 G27 U10.P4, U2.F2
U3.J11 Data bus FSM_D1 F28 U10.R1, U2.E2
U3.K10 Data bus FSM_D2 E28 U10.P5, U2.G3
U3.K11 Data bus FSM_D3 D30 U10.T2, U2.E4
U3.L10 Data bus FSM_D4 C30 U10.N5, U2.E5
U3.L11 Data bus FSM_D5 F29 U10.R3, U2.G5
U3.M10 Data bus FSM_D6 E29 U10.P6, U2.G6