Altera Stratix IV E FPGA Development Board - Manual (Page 52)

2–44 Chapter 2: Board Components
Memory
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
J20.123 Data bus DDR3_DIMM_DQ5
1.5-V SSTL Class I
AJ27
J20.128 Data bus DDR3_DIMM_DQ6 AH27
J20.129 Data bus DDR3_DIMM_DQ7 AJ26
J20.12 Data bus DDR3_DIMM_DQ8 AP32
J20.13 Data bus DDR3_DIMM_DQ9 AP30
J20.18 Data bus DDR3_DIMM_DQ10 AP31
J20.19 Data bus DDR3_DIMM_DQ11 AN31
J20.131 Data bus DDR3_DIMM_DQ12 AH26
J20.132 Data bus DDR3_DIMM_DQ13 AF24
J20.137 Data bus DDR3_DIMM_DQ14 AH25
J20.138 Data bus DDR3_DIMM_DQ15 AF23
J20.21 Data bus DDR3_DIMM_DQ16 AM28
J20.22 Data bus DDR3_DIMM_DQ17 AP29
J20.27 Data bus DDR3_DIMM_DQ18 AP27
J20.28 Data bus DDR3_DIMM_DQ19 AN27
J20.140 Data bus DDR3_DIMM_DQ20 AK27
J20.141 Data bus DDR3_DIMM_DQ21 AL28
J20.146 Data bus DDR3_DIMM_DQ22 AK25
J20.147 Data bus DDR3_DIMM_DQ23 AM26
J20.30 Data bus DDR3_DIMM_DQ24 AK24
J20.31 Data bus DDR3_DIMM_DQ25 AL25
J20.36 Data bus DDR3_DIMM_DQ26 AM23
J20.37 Data bus DDR3_DIMM_DQ27 AL23
J20.149 Data bus DDR3_DIMM_DQ28 AH23
J20.150 Data bus DDR3_DIMM_DQ29 AJ24
J20.155 Data bus DDR3_DIMM_DQ30 AJ23
J20.156 Data bus DDR3_DIMM_DQ31 AK22
J20.81 Data bus DDR3_DIMM_DQ32 AM21
J20.82 Data bus DDR3_DIMM_DQ33 AP20
J20.87 Data bus DDR3_DIMM_DQ34 AP21
J20.88 Data bus DDR3_DIMM_DQ35 AN21
J20.200 Data bus DDR3_DIMM_DQ36 AL22
J20.201 Data bus DDR3_DIMM_DQ37 AM22
J20.206 Data bus DDR3_DIMM_DQ38 AJ20
J20.207 Data bus DDR3_DIMM_DQ39 AJ21
J20.90 Data bus DDR3_DIMM_DQ40 AH15
J20.91 Data bus DDR3_DIMM_DQ41 AJ15
J20.96 Data bus DDR3_DIMM_DQ42 AG15
Table 2–43. DDR3 Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)
Board
Reference
Description
Schematic Signal Name
I/O Standard
Stratix IV E
Device
Pin Number