Altera Stratix IV E FPGA Development Board - Manual (Page 67)

Chapter 2: Board Components 2–59
Power Supply
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
Power Measurement
There are 12 power supply rails which have on-board voltage and current sense
capabilities. These 8-channel differential 24-bit ADC devices and rails are split from
the primary supply plane by a low-value sense resistor for the ADC to measure
voltage and current. A SPI bus connects these ADC devices to the MAX II CPLD
EPM2210 System Controller.
Figure 2–10 shows the block diagram for the power measurement circuitry.
Table 2–53 lists the targeted rails. The schematic signal name column specifies the
name of the rail being measured and the device pin column specifies the devices
attached to the rail. If no subnet is named, the power is the total output power for that
voltage.
Figure 2–10. Power Measurement Circuit
SCK
DSI
DSO
CSn
8 Ch.
To Plane 0x0
To Plane 0xE
Supply
0x0
Supply
0xE
R
SENSE
R
SENSE
SCK
DSI
DSO
CSn
8 Ch.
EPM2210 EP4SE530
LTC2418
LTC2418
U44
EPM
240
USB
PHY
To User PC
Power GUI
JTAG Chain
SPI Bus
Embedded
USB-Blaster
To Plane 0xF
12-V
Supply
R
SENSE
SCL
SDA
1 Ch.
LTC4151
SM Bus
U21
U43
Table 2–53. Power Rail Measurements Based on the Rotary Switch Position (Part 1 of 2)
Switch Schematic Signal Name Voltage (V) Device Pin Description
0 1.5V_1.8V_B7 1.5 VCCIO_B7 Bank 7 I/O power (QDRII)
1 2.5V_B5_B6 2.5
VCCIO_B5 Bank 5 I/O power (HSMC port A)
VCCIO_B6 Bank 6 I/O power (HSMC port B)
2 1.5V_DDR3 1.5
VCCIO_B3 Bank 3 I/O power (DDR3 memory)
VCCIO_B4A Bank 4A I/O power (DDR3 memory)
VCCIO_B4C Bank 4C I/O power (DDR3 memory)