Altera Stratix IV E FPGA Development Board User Manual
Page 51

Chapter 2: Board Components
2–43
Memory
May 2011
Altera Corporation
Stratix IV E FPGA Development Board Reference Manual
J20.177
Address bus
DDR3_DIMM_A8
1.5-V SSTL Class I
AP19
J20.175
Address bus
DDR3_DIMM_A9
AK18
J20.70
Address bus
DDR3_DIMM_A10
AP15
J20.55
Address bus
DDR3_DIMM_A11
AL20
J20.174
Address bus
DDR3_DIMM_A12
AK19
J20.196
Address bus
DDR3_DIMM_A13
AF16
J20.172
Address bus
DDR3_DIMM_A14
AE18
J20.171
Address bus
DDR3_DIMM_A15
AD19
J20.71
Bank address bus
DDR3_DIMM_BA0
AM15
J20.190
Bank address bus
DDR3_DIMM_BA1
AM16
J20.52
Bank address bus
DDR3_DIMM_BA2
AK16
J20.74
Column address strobe
DDR3_DIMM_CASn
AK13
J20.50
Clock enable 0
DDR3_DIMM_CKE0
AJ16
J20.169
Clock enable 1
DDR3_DIMM_CKE1
AD18
J20.185
Differential output clock 0
complement
DDR3_DIMM_CLK_N0
Differential 1.5-V
SSTL Class I
AJ8
J20.64
Differential output clock 1
complement
DDR3_DIMM_CLK_N1
AK7
J20.184
Differential output clock 0
DDR3_DIMM_CLK_P0
AH8
J20.63
Differential output clock 1
DDR3_DIMM_CLK_P1
AJ7
J20.193
Chip select
DDR3_DIMM_CSn0
1.5-V SSTL Class I
AL16
J20.76
Chip select
DDR3_DIMM_CSn1
AE16
J20.79
Chip select
DDR3_DIMM_CSn2
AD15
J20.198
Chip select
DDR3_DIMM_CSn3
AD16
J20.125
Data write mask bit 0 (byte enables)
DDR3_DIMM_DM0
AJ28
J20.134
Data write mask bit 1 (byte enables)
DDR3_DIMM_DM1
AG24
J20.143
Data write mask bit 2 (byte enables)
DDR3_DIMM_DM2
AL26
J20.152
Data write mask bit 3 (byte enables)
DDR3_DIMM_DM3
AH22
J20.203
Data write mask bit 4 (byte enables)
DDR3_DIMM_DM4
AK21
J20.212
Data write mask bit 5 (byte enables)
DDR3_DIMM_DM5
AN12
J20.221
Data write mask bit 6 (byte enables)
DDR3_DIMM_DM6
AK9
J20.230
Data write mask bit 7 (byte enables)
DDR3_DIMM_DM7
AL5
J20.161
Data write mask bit 8 (byte enables)
DDR3_DIMM_DM8
AF21
J20.3
Data bus
DDR3_DIMM_DQ0
AL29
J20.4
Data bus
DDR3_DIMM_DQ1
AM29
J20.9
Data bus
DDR3_DIMM_DQ2
AN30
J20.10
Data bus
DDR3_DIMM_DQ3
AM30
J20.122
Data bus
DDR3_DIMM_DQ4
AJ29
Table 2–43. DDR3 Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)
Board
Reference
Description
Schematic Signal Name
I/O Standard
Stratix IV E
Device
Pin Number