Altera Stratix IV E FPGA Development Board - Manual (Page 20)

2–12 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
Table 2–6 lists the MAX II CPLD EPM2210 System Controller component reference
and manufacturing information.
Configuration, Status, and Setup Elements
This section describes the board's configuration, status, and setup elements.
Configuration
This section describes the FPGA, flash memory, and MAX II CPLD EPM2210 System
Controller device programming methods supported by the Stratix IV E FPGA
development board. The Stratix IV E FPGA development board supports the
following three configuration methods:
■ Embedded USB-Blaster is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied USB cable.
■ Flash memory programming using the Board Update Portal factory design.
■ FPGA Programming from Flash memory for configuring the FPGA using stored
images from the flash memory on either power-up or pressing the reset
configuration push-button switch (S1).
FPGA Programming over Embedded USB-Blaster
The USB-Blaster is implemented using a USB Type-B connector (J6), a FTDI USB 2.0
PHY device (U7), and an Altera MAX II CPLD (U10). This allows the configuration of
the FPGA using a USB cable directly connected between the USB port on the board
(J6) and a USB port of a PC running the Quartus II software. The JTAG chain is
normally mastered by the embedded USB-Blaster found in the MAX
II CPLD
EPM2210 System Controller.
Table 2–6. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information
Board Reference Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U10
IC - MAX II CPLD EPM2210
256FBGA -3 LF 2.5V VCCINT
Altera Corporation EPM2210F256C3N www.altera.com