Altera Stratix IV E FPGA Development Board - Manual (Page 43)

Chapter 2: Board Components 2–35
Components and Interfaces
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
J19.7 Transceiver TX bit 6n
NC 1.4-V PCML
— —
J19.8 Transceiver RX bit 6n — —
J19.9 Transceiver TX bit 5 — —
J19.10 Transceiver RX bit 5 — —
J19.11 Transceiver TX bit 5n — —
J19.12 Transceiver RX bit 5n — —
J19.13 Transceiver TX bit 4 — —
J19.14 Transceiver RX bit 4 — —
J19.15 Transceiver TX bit 4n — —
J19.16 Transceiver RX bit 4n — —
J19.17 Transceiver TX bit 3 — —
J19.18 Transceiver RX bit 3 — —
J19.19 Transceiver TX bit 3n — —
J19.20 Transceiver RX bit 3n — —
J19.21 Transceiver TX bit 2 — —
J19.22 Transceiver RX bit 2 — —
J19.23 Transceiver TX bit 2n — —
J19.24 Transceiver RX bit 2n — —
J19.25 Transceiver TX bit 1 — —
J19.26 Transceiver RX bit 1 — —
J19.27 Transceiver TX bit 1n — —
J19.28 Transceiver RX bit 1n — —
J19.29 Transceiver TX bit 0 — —
J19.30 Transceiver RX bit 0 — —
J19.31 Transceiver TX bit 0n — —
J19.32 Transceiver RX bit 0n — —
J19.33 Management serial data HSMA_SDA
2.5-V
V3 —
J19.34 Management serial clock HSMA_SCL Y2 —
J19.35 JTAG clock signal JTAG_TCK — —
J19.36 JTAG mode select signal JTAG_TMS — —
J19.37 JTAG data output HSMA_JTAG_TDO — —
J19.38 JTAG data input HSMA_JTAG_TDI — —
J19.39 Dedicated CMOS clock out HSMA_CLK_OUT0 W11 —
J19.40 Dedicated CMOS clock in HSMA_CLK_IN0 B20 —
J19.41 Dedicated CMOS I/O bit 0 HSMA_D0 AL10 —
J19.42 Dedicated CMOS I/O bit 1 HSMA_D1 AL11 —
J19.43 Dedicated CMOS I/O bit 2 HSMA_D2 AN7 —
J19.44 Dedicated CMOS I/O bit 3 HSMA_D3 AP7 —
Table 2–40. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)
Board
Reference
Description
Schematic Signal
Name
I/O Standard
Stratix IV E
Device
Pin Number
Other
Connections