Altera QDRII SRAM Controller MegaCore Function - Manual (Page 58)

3–26 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009
Device-Level Configuration
Device-Level
Configuration This section describes the following topics:
■ “PLL Configuration” on page 3–26
■ “Example Design” on page 3–27
■ “Constraints” on page 3–29
PLL Configuration
IP Toolbench creates up to two example PLLs in your project directory,
which you can parameterize to meet your exact requirements. IP
Toolbench generates the example PLLs with an input to output clock ratio
of 1:1 and a clock frequency you entered in IP Toolbench. In addition IP
Toolbench sets the correct phase outputs on the PLLs’ clocks. You can
edit the PLLs to meet your requirements with the altpll MegaWizard
Plug-In. IP Toolbench overwrites your PLLs in your project directory
unless you turn off the Reset PLL to default setting option.
The external clocks are generated using standard I/O pins in double data
rate I/O (DDIO) mode (using the altddio_out megafunction). This
generation matches the way in which the write data is generated and
allows better control of the skew between the clock and the data to meet
the timing requirements of the QDRII SRAM.
The PLL has the following outputs:
■ Output c0 drives the system clock that clocks most of the controller
including the state machine and the local interface.
■ Output c1 drives the write clock that lags the system clock by 90.
The recommended configuration for implementing the QDRII SRAM
controller in a Stratix series is to use a single enhanced PLL to produce all
the required clock signals. No external clock buffer is required as the
Altera device can generate clock signals for the QDRII SRAM devices.
For Stratix II devices, if you turn off DQS mode, you enable fed-back
resynchronization, which uses a fed-back clock to resynchronize the data.
Figure 3–20 on page 3–27 shows the recommended PLL configuration.