Altera QDRII SRAM Controller MegaCore Function - Manual (Page 40)

3–8 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009
Block Description
With more than one device, one cq/cqn pair and q bus are connected per
device in the width direction. For a device depth of two, it shares the q
and cq/cqn signals.
All the signals go out of the block with their associated internal cq clock,
so you can use Altera's resynchronization scheme or implement your
own.
Altera recommends the following read capture implementation for data
captures from QDRII SRAM devices when using complementary echo
clocks (cq and cqn signals).
The Stratix II IOE contains two input registers and a latch. The cq and
cqn
echo clock signals clock the positive and negative half-cycle registers
during reads. The latch holds the negative half-cycle data until the next
rising edge on cq. However, the latch in the IOE is not recommended
when the complementary clocks do not have 50% duty cycle or skew,
because the latch, controlled by the cq clock, is still transparent until just
after the register clocked on the cqn signal captures the data.
Instead, the captured read data is recaptured with the cq echo clock in the
FPGA fabric using a zero-cycle path. The cq echo clock is routed into the
FPGA fabric using dedicated clock routing (Altera recommends global
routing) to provide minimum clock skew across all recapture registers. If
you do not have enough global clock network resources, you have the
option of using the regional clock network. Routing the cq over a clock
network adds delay. The Quartus II software fitter places and routes the
recapture registers so that the data delay is sufficient to meet the setup
and hold requirements at the device registers.
1
You should only use regional routing if you run out of the global
clock networks.
Figure 3–5 shows a block diagram of the new read capture
implementation.