Altera QDRII SRAM Controller MegaCore Function - Manual (Page 38)

3–6 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009
Block Description
Figure 3–4. Datapath Block Diagram
Clock
Generator
Address & Command
Output Registers
Capture Group
Modules
To Resynchronization
Write
Registers
From Write FSM
Write
Registers
From Control Logic
Address &
Command
Output
Registers
Address &
Command
Output
Registers
Read
Capture
Registers
CQ/CQN
Group
Read
Capture
Registers
CQ/CQN
Group
Datapath