Altera QDRII SRAM Controller MegaCore Function User Manual
Page 16
2–6
MegaCore Version 9.1
Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide
November 2009
QDRII SRAM Controller Walkthrough
4.
Click Board & Controller tab or Next.
f
For more information on board and controller parameters, refer to
“Board & Controller” on page 3–31
5.
Choose the number of pipeline registers.
6.
To set the read latency, turn on Manual read latency setting and
specify the latency at Set latency to clock cycle.
7.
Turn on the appropriate capture mode—DQS or non-DQS capture
mode. If you turn off Enable DQS mode (non-DQS capture mode),
you can turn on Use migratable bytegroups.
8.
Enter the pin loading for the FPGA pins.
9.
Click Project Settings tab or Next.
f
For more information on the project settings, refer to
.
10. Altera recommends that you turn on Automatically apply QDRII
SRAM controller-specific constraints to the Quartus II project
so
that the Quartus II software automatically applies the constraints
script when you compile the example design.
11. Ensure Update the example design that instantiates the QDRII
SRAM controller variation
is turned on, for IP Toolbench to
automatically update the example design file.
12. Turn off Update example design system PLL, if you have edited the
PLL and you do not want the wizard to regenerate the PLL when
you regenerate the variation.
1
The first time you create a custom variation, you must turn
on Update example design system PLL.
13. The constraints script automatically detects the hierarchy of your
design. The constraints script analyzes and elaborates your design
to automatically extract the hierarchy to your variation. To prevent
the constraints script analyzing and elaborating your design, turn
on Enable hierarchy control, and enter the correct hierarchy path to
your variation. The hierarchy path is the path to your QDRII SRAM
controller, without the top-level name.
shows the
following example hierarchy:
my_system:my_system_inst|sub_system:sub_system_inst|