Altera QDRII SRAM Controller MegaCore Function User Manual
Page 10
1–6
MegaCore Version 9.1
Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide
November 2009
Performance and Resource Utilization
shows typical sizes in combinational adaptive look-up tables
(ALUTs) and logic registers for a QDRII SRAM controller with a burst
length of 4 in narrow mode.
Table 1–7. Typical Size
Device
Memory Width (Bits)
Combinational
ALUTs
Logic
Registers
Memory Blocks
M4K
M512
Stratix II
9
360
598
–
1
18
369
633
1
–
36
390
708
2
–
72 (2 × 36)
459
880
4
–
Notes to
:
(1)
These sizes are a guide only and vary with different choices of parameters.
See also other documents in the category Altera Measuring instruments:
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
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- Hybrid Memory Cube Controller (69 pages)
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- MAX 10 Embedded Memory (71 pages)
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- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
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- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)