Altera QDRII SRAM Controller MegaCore Function - Manual (Page 12)

2–2 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009
QDRII SRAM Controller Walkthrough
1
IP Toolbench is a toolbar from which you quickly and easily
view documentation, specify parameters, and generate all
of the files necessary for integrating the parameterized
MegaCore function into your design.
3. Implement the rest of your design using the design entry method of
your choice.
4. Use the IP Toolbench-generated IP functional simulation model to
verify the operation of your design.
f
For more information on IP functional simulation models, refer to the
Simulating Altera IP in Third-Party Simulation Tools chapter in volume 3 of
the Quartus II Handbook.
5. Edit the PLL(s).
6. Use the Quartus II software to add constraints to the example
design and compile the example design.
7. Perform gate-level timing simulation, or if you have a suitable
development board, you can generate an OpenCore Plus
time-limited programming file, which you can use to verify the
operation of the example design in hardware.
8. Either obtain a license for the QDRII SRAM controller MegaCore
function or replace the encrypted QDRII SRAM controller control
logic with your own logic and use the clear-text data path.
1
If you obtain a license for the QDRII SRAM controller, you
must set up licensing.
9. Generate a programming file for the Altera device(s) on your board.
10. Program the Altera device(s) with the completed design.
QDRII SRAM
Controller
Walkthrough This walkthrough explains how to create a QDRII SRAM controller using
the Altera QDRII SRAM controller IP Toolbench and the Quartus II
software. When you are finished generating a custom variation of the
QDRII SRAM Controller MegaCore function, you can incorporate it into
your overall project.
1 IP Toolbench only allows you to select legal combinations of
parameters, and warns you of any invalid configurations.
This walkthrough requires the following steps: