Altera QDRII SRAM Controller MegaCore Function User Manual
Page 30
2–20
MegaCore Version 9.1
Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide
November 2009
Compile the Example Design
b.
Use the DDR timing wizard (DTW) to generate the required
QDRII SRAM Synopsys design constraint (SDC) TimeQuest
constraints for the design.
f
For more information on the DTW, refer to the
2.
Choose Start Compilation (Processing menu), which runs the add
constraints scripts, compiles the example design, and performs
timing analysis.
3.
View the Classic or TimeQuest Timing Analyzer to verify your
design meets timing.
If your design does not meet timing requirements, add the following lines
to you .qsf file:
set_instance_assignment -name GLOBAL_SIGNAL OFF -to soft_reset_n
set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING ON
If the compilation does not reach the frequency requirements, follow
these steps:
1.
Choose Settings (Assignments menu).
2.
Choose Analysis and Synthesis Settings in the category list.
3.
Select Speed in Optimization Technique.
4.
Click OK.
5.
Re-compile the example design by choosing Start Compilation
(Processing menu).
To view the constraints in the Quartus II Assignment Editor, choose
Assignment Editor
(Assignments menu).
1
If you have “?” characters in the Quartus II Assignment Editor,
the Quartus II software cannot find the entity to which it is
applying the constraints, probably because of a hierarchy
mismatch. Either edit the constraints script, or enter the correct
hierarchy path in the Hierarchy tab (refer to step
on
).
f
For more information on constraints, refer to
.